Japanese Patent Application No. 2001-141616, filed May 11, 2001, is hereby incorporated by reference in its entirety.
1. Technical Field
The present invention relates to a programming method for a non-volatile semiconductor memory device formed from twin memory cells each being equipped with one word gate and two non-volatile memory elements controlled by two control gates.
2. Background
There is known a MONOS (Metal-Oxide-Nitride-Oxide-semiconductor or -substrate) type non-volatile semiconductor device in which a gate dielectric layer between a channel and a gate is formed from a stacked body including a silicon oxide film, a silicon nitride film, and a silicon oxide film, and charge is trapped in the silicon nitride film.
A MONOS type non-volatile semiconductor memory device is described in a reference (Y. Hayashi, et al. 2000 Symposium on VLSI Technology, Digest of Technical Papers, p. 122-p. 123). The reference describes a twin MONOS flash memory cell equipped with one word gate and two non-volatile memory elements (MONOS memory elements) controlled by two control gates. In other words, one flash memory cell includes two charge trap sites.
A plurality of twin MONOS flash memory cells each having the structure described above are arranged in the row direction and the column direction in multiple rows and columns to form a memory cell array region.
Two bit lines, one word line, and two control gate lines are required to drive a MONOS flash memory cell. However, when driving a plurality of twin memory cells, these lines can be commonly connected for different control gates if they are set at the same potential.
Operations of this type of flash memory include erasing, programming, and reading data. Normally, data programming or data reading is performed at selected cells in units of 8 bits or 16 bits simultaneously.
It is noted that, in the MONOS flash memory, a plurality of twin MONOS flash memory cells that are not mutually isolated are connected to one word line. For programming data at a specified selected cell (selected non-volatile memory element), not only must the voltage of a twin MONOS flash memory including the selected cell be appropriately set, but also the voltage of an adjacent twin MONOS flash memory cell must be appropriately set.
Therefore, it is an object of the present invention to provide a programming method for a non-volatile semiconductor memory device, in which, when data is programmed at a selected cell, voltages are appropriately set for a twin memory cell including the selected cell and an adjacent twin memory cell such that data can be reliably programmed at the selected cell.
In accordance with one embodiment of the present invention, a programming method in which a plurality of twin memory cells, each having one word gate and first and second non-volatile memory elements controlled by first and second control gates, are arranged and, from among three adjacent twin memory cells (ixe2x88x921), (i), and (i+1) whose word gates are connected to one word line, data for the second non-volatile memory element of the twin memory cell (i) is programmed, comprises:
setting the word line to a programming word line selection voltage;
setting the second control gate of the twin memory cell (i) and the first control gate of the twin memory cell (i+1) to a programming control gate voltage;
setting the second control gate of the twin memory cell (ixe2x88x921) and the first control gate of the twin memory cell (i) to an over-ride voltage;
setting a bit line commonly connected to the second non-volatile memory element of the twin memory cell (i) and the first non-volatile memory element of the twin memory cell (i+1) to a programming bit line voltage; and
connecting a bit line that is commonly connected to the second non-volatile memory element of the twin memory cell (ixe2x88x921) and the first non-volatile memory element of the twin memory cell (i) to a constant current source.
In accordance with another embodiment of the present invention, a programming method in which a plurality of twin memory cells, each having one word gate and first and second non-volatile memory elements controlled by first and second control gates, are arranged and, from among three adjacent twin memory cells (ixe2x88x921), (i), and (i+1) whose word gates are connected to one word line, data for the first non-volatile memory element of the twin memory cell (i) is programmed, comprises:
setting the word line to a programming word line selection voltage;
setting the second control gate of the twin memory cell (ixe2x88x921) and the first control gate of the twin memory cell (i) to a programming control gate voltage;
setting the second control gate of the twin memory cell (i) and the first control gate of the twin memory cell (i+1) to an over-ride voltage;
setting a bit line commonly connected to the second non-volatile memory element of the twin memory cell (ixe2x88x921) and the first non-volatile memory element of the twin memory cell (i) to a programming bit line voltage; and
connecting a bit line that is commonly connected to the second non-volatile memory element of the twin memory cell (i) and the first non-volatile memory element of the twin memory cell (i+1) to a constant current source.
In both of the embodiments described above, current that flows in the bit line at the time of programming is restricted by the constant current source, such that the voltage for the bit line can be properly set and the programming operation can be securely performed.
It is noted that the programming word line selection voltage may preferably be set to a voltage that is high enough to be able to cause a current greater than a current provided by the constant current source to flow between a source and a drain (between bit lines) of the selected twin memory cell. As a result, the current that flows in the bit line during programming is also restricted at a constant level by the constant current source, such that the voltage for the bit line can be properly set and the programming operation can be securely performed.
Each of the first and second non-volatile memory elements may include an ONO film formed from an oxide film (O), a nitride film (N), and an oxide film (O), which can be used as a charge trap site, but can have any other structure without being restricted to the structure described above.